Industrial Seminars 4:
New console architectures
Thursday, September 1st, 2005. 11:00-12:30.
VENUE: Beckett Rooms Walton Theatre
Overview of the Xbox360 GPU
Michael Doggett, ATI
The Xbox360 GPU unifies the traditional vertex and pixel shaders of
the graphics pipeline enabling the GPU to dynamically balance
resources between these two stages. The GPU system consists of two
separate devices, the majority of the pipeline is on one die with a
second die containing just the Z and Alpha blending operations coupled
with embedded memory and utilizing a very wide memory interface. The
GPU offers support for Higher Order Surfaces and an advanced
shading instruction set including the ability to randomly write data
to memory.
Cell processor architecture and programming
Kevin O'Brien, IBM Research
The Cell processor, featured in the recently announce Sony Playstation 3
and jointly developed by Sony, Toshiba and IBM is particularly suited to
the high performance demands of the gaming and multimedia application
areas, but may also be attractive in other fields of high performance
computing. The chip combines a PowerPC core (PPE) with 8
Synergistic Processing Elements (SPE) to form a heterogeneous, single chip
multi-processor. Each of the SPE's consists of a 128 bit wide SIMD
processor coupled with a fast Local Store which contains the program and
data for the processor. Also on the chip is a coherent bus supporting DMA
transactions between the Local Stores of the SPEs, and system memory.
Programming to take the best advantage of the Cell processor requires
partitioning the application across the different processor types, and two
levels of parallelization, one to leverage the 8 SPE cores, and the other
to exploit the 4-way SIMD capabilities of those processors. In addition,
the orchestration of data into and out of the SPE Local Stores is of prime
importance. This talk will cover the broad outlines of the architecture,
and share some insights into programming for this chip gained in the
development of a prototype C compiler for the architecture.
The Eurographics'05 organisers and IBM Research would like to
acknowledge the kind support of IBM Ireland in organising this talk.
NVIDIA game console technology
Henry Moreton, NVIDIA
abstract to follow
Biographies
Michael Doggett works as an architect on graphics hardware at ATI
Research. He has recently worked on the XBox360 GPU and is currently
working on future PC graphics. He studied at The University of New
South Wales, Sydney, Australia and the University of Tuebingen,
Germany. He has been involved in the organisation of the Graphics
Hardware workshop and has given presentations at SIGGRAPH and the Game
Developers Conference.
Kevin O'Brien has spent the last 24 years at IBM working in the field of
compilation and architecture.
Initially, at the IBM Toronto Lab, he was the architect of the TOBEY
optimizing backend (used in
IBM's xlc, xlf, and xlC (C++) product compilers). Subsequently, Kevin has
spent 17 years at IBM
Research, where his research interests have included Multithreaded
Architecture, Smalltalk, Java,
continuous optimization, binary translation and optimization,
parallelization and vectorization
(including SIMDization), for several processors, most recently the Cell
processor. He has also
contributed to the architectures of Power, PowerPC and Cell. Currently,
Kevin is investigating memory
related optimizations for the Cell processor.
Henry Moreton joined NVIDIA in the fall of 1998 as a member of the architecture
group. From 1984 to 1998 he worked at Silicon Graphics. In 1992 he received a Ph.D.
from the University of California, Berkeley. He has published in the areas of curve
and surface modeling, rendering, texture mapping, video and image compression, and
unmanned submarine control. He has more than twenty five patents in the areas of
optics, video compression, graphics, system and CPU architecture, and curve &
surface modeling & rendering. Current interests include evolution of graphics
programming models and, API design and hardware architecture of highly parallel
programmable devices.
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